When manufacturing semiconductor devices, the processes of forming a thin film on a silicon substrate and lithographing and patterning the thin film by dry etching are repeatedly carried out, and the silicon substrate itself is often dry-etched at the initial stage of the manufacturing processes.
Dry etching of the silicon substrate is mainly carried out for trench formation in silicon, e.g., groove-shaped trenches for device isolation and hole-shaped trenches for capacitor formation. In etching silicon trenches, it is important to control the depth to width ratio (i.e. aspect ratio) and a vertical cross sectional shape of the trench; and especially it is an important issue to prevent bowing, which is a barrel-shaped hollow portion of an inner wall of the trench, and undercut etching below a mask (i.e. side etching) and the like. To solve such technical issue, the etching gas employs a halogen compound gas including hydrogen, such as hydrogen bromide (HBr), or a gaseous mixture in which CHF3 or the like is added to a halogen gas such as Cl2. As for an etching apparatus, a reactive ion etching (RIE) apparatus is employed, which gives the directivity to ions in the plasma and allows the ions to react with a target object (silicon substrate) (see, e.g., the Japanese Patent Laid-open Application No. 2003-218093).
With ever-increasing demands for high-integration and high-performance of the semiconductor devices manufactured on the silicon substrate, semiconductor elements constituting the devices are made smaller by a scaling rule of about 0.7-times. Therefore, 65 nm and 45 nm design rule (i.e. design standard), which are currently applied to the state-of-the-art semiconductor products, are expected to become about 32 nm in the next-generation products and about 22 nm in the next-next generation products.
If the device design standard approaches to 22 nm in the next-next generation products, a metal insulator semiconductor field effect transistor (MISFET), which is a basic semiconductor device for the large scale integration (LSI) circuits, is highly likely to be changed from a two-dimensional structure (planar structure), in which its channel, source and drain regions are two-dimensionally formed on a main surface of a silicon substrate, to a three-dimensional structure (stereoscopic structure), in which such regions are three-dimensionally formed on the main surface of the silicon substrate.
In the three-dimensional structure, the channel region is formed on a sidewall of a fin or a pillar, which may protrude and extend above the main surface of the silicon substrate, and the source and drain regions are formed at opposite sides of the channel region in the channel length direction. Here, a three-dimensional element body such as the fin or the pillar may be obtained by etching the main surface of the silicon substrate down to a depth of 100 nm or more.
In the etching process of such a three-dimensional element, it is an important issue to minimize the damage to an etched sidewall of a target object and prevent an undesirable groove (a microtrench) from being formed in a lower end portion of the etched sidewall (a lower portion of the main body). In other words, the etched sidewall in this process is employed as the channel region of the MISFET, unlike in the case of a conventional trench etching. Accordingly, if ions are incident on the sidewall, and thus the crystal lattice at the surface region thereof is damaged, the mobility of electrons or holes (charge carriers) is decreased and the performance of the MISFET is significantly deteriorated. Further, if the microtrench is formed at a lower portion of the pillar, such microtrench tends to hinder the formation of an impurity region (the source or the drain region). The accuracy in a vertical shape of the sidewall of the target object is also required for the stability and the reproducibility of the performance of the MISFET.